1. Field of the Invention
The present invention relates to methods for fabricating electrical connecting elements such as Printed Circuit Boards (PCBs), High-Density-Interconnects (HDIs), Ball-Grid-Array (BGA) substrates, Chip Scale Packages (CSP), Multi-Chip-Module-(MCM) substrates, etc. The present invention also relates to an electrical connecting element and to an apparatus for fabricating electrical connecting elements.
2. Description of Related Art
In modern circuit board technology, due to increasing miniaturization, conventionally drilled through holes are increasingly being replaced by microvias. Methods for fabricating such microvias include laser drilling and plasma drilling as well as photochemical structuring. A new method for fabricating microvias has been disclosed in WO 00/13062. This new technology approach, the Micro-Perforation, is a method including mechanical embossing of micro-holes into deformable dielectric material. With Micro-Perforation, any shape of a microvia is feasible. By controlling the length and size of perforation-tips also the formation of very small blind microvias can be achieved.
However, the fabrication of blind microvias by Micro-Perforation and the other state of the art methods have in common that a via fabricating step has to be followed by a contacting step between the conducting layers or pads across the via. Depending on the microvia geometry, such a contacting step may be a chemical or physical deposition of some conductor material as a seed layer followed by an electroplating step. Plating of very small blind holes of 100 μm diameter and less is very tricky and often results in non-plated holes and consequently scrapped boards. Also, incomplete plating of sidewalls of the holes affects the reliability of the boards.
If, according to the state of the art, a build-up of three, four or more layers is produced, in a first step a core consisting of two conducting and structured layers separated by a dielectric substrate layer with vias is provided. Then, dielectric layers, which are coated on one side by a metal layer, are subsequently laminated on the core, perforated, plated, and structured. This procedure even enhances the impact of the above-mentioned shortcomings of the present lamination method. Testing of the via reliability and the quality of the structuring of the outermost layer is only possible after the latter has been laminated to the core and structured. If a via side wall is incompletely plated, the entire board has to be scrapped, including a possibly perfect core.
It therefore would be desirable to have a method that makes this plating step more reliable and leads to a reduction of production cost and of environmental impact caused by wet chemical bathes. Preferably, the method should also make more efficient testing possible and prevent the situation that an entire board including perfect parts has to be scrapped.